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Diane Publishing Books
Electro-Physical Technique for Post-Fabrication Measurements of CMOS Process Layer Thickness: A Reprint from “Journal of Research of the NIST”
Janet C. Marshall (au); P. Thomas Vernier (au)
Presents a combined physical & electrical post-fabrication method for determining the thicknesses of the various layers in a commercial 1.5 um complementary-metal-oxide-semiconductor foundry process available through MOSIS. 42 thickness values are obtained from physical step-height measurements performed on thickness test structures & from electrical measurements of capacitances, sheet resistances, & resistivities. Appropriate expressions, numeric values, & uncertainties for each layer of thickness are presented, along with a systematic nomenclature for interconnect & dielectric thicknesses. Inconsistencies between the physical & electrical results for film thickness suggest that further uncertainty analysis is required. Illustrations.
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